It is our application requirement, in idle mode, to keep the device in
minimum possible power consumption mode in which the device remains registered
on the network and reachable for incoming calls or SMS. I have achieved
this using +CFUN = 0 or 5.
The
problem is that i want the device to come out of the power sqaving mode
whenever there is a low to high or high to low change on any of the GPIO pin
but it is not working like this."I also understand the
first wake-up event, or rising RTS line, stops power saving and takes the ME
back to full functionality level <fun>=1 "
Attach is the logical setion that is responsible for generating a pulse on RTS line in board.
Circuit explanation:
– SN74LVC86 is Ex-OR gate IC.
– IGN I/P, SIM-IP & EX – I/P are the three input signals. On a change on any of these signal lines I want GL-865 to wake up.
– In first stage, IGN I/P & SIM-IP are Ex-Ored and hence any change will generate a change in output.
– With help of RC circuit and Ex-Or gate this change in signal is converted into a pulse Low(0V) – High(2.8V) – Low(0V). Same is done with EX – I/P signal in the third stage.
– Finally the pulses from second and third stage are Ex-ORed to give a final pulse on RTS line. As the possibility of a simultaneous change on any two signal lines is negligible i dont need to worry about such circumstances.
– The RC time constant is such adjusted that we get a minimum 1 sec pulse on RTS line. We have decide for 1 sec after many practical observations on RTS line.
Hi,
It is our application requirement, in idle mode, to keep the device in
minimum possible power consumption mode in which the device remains registered
on the network and reachable for incoming calls or SMS. I have achieved
this using +CFUN = 0 or 5.
The
problem is that i want the device to come out of the power sqaving mode
whenever there is a low to high or high to low change on any of the GPIO pin
but it is not working like this."I also understand the
first wake-up event, or rising RTS line, stops power saving and takes the ME
back to full functionality level <fun>=1 "
Attach is the logical setion that is responsible for generating a pulse on RTS line in board.
Circuit explanation:
– SN74LVC86 is Ex-OR gate IC.
– IGN I/P, SIM-IP & EX – I/P are the three input signals. On a change on any of these signal lines I want GL-865 to wake up.
– In first stage, IGN I/P & SIM-IP are Ex-Ored and hence any change will generate a change in output.
– With help of RC circuit and Ex-Or gate this change in signal is converted into a pulse Low(0V) – High(2.8V) – Low(0V). Same is done with EX – I/P signal in the third stage.
– Finally the pulses from second and third stage are Ex-ORed to give a final pulse on RTS line. As the possibility of a simultaneous change on any two signal lines is negligible i dont need to worry about such circumstances.
– The RC time constant is such adjusted that we get a minimum 1 sec pulse on RTS line. We have decide for 1 sec after many practical observations on RTS line.
Thanks,
KD