Hi, I’ve just built an prototype PCB, using a JN3 for my GPS reciever. I am having some issues with patch antennas with integrated LNA, in that some appear to function with the design and I achieve lock, others have no signal level.
I would like to double check the layout with a known good reference to see what I missed. I am runnung the JN3 at 2v8, but this should be ok from section 2.1 in the JN3 userguide.
Is a full schematic and layout avaiable of the diagram in section 3.2 of the Eval board user manual?
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