GL865 footprint inhibit area change

5 thoughts on “GL865 footprint inhibit area change

  1. Hi,


    I’ve noticed that since rev 7. (2014-4-2) "gl865 hardware user guide" changed the inhibit area under the module (chapter 13.3).

    The note is very short: "the region under WIRING INHIBIT must be clear from signal or ground paths".


    I’m designing a 2 layers FR4 (1,6mm) PCB.


    I guess I need a "hole" of 2mm in the copper area under  the module in this 4 locations.


    But, are this inhibit areas also requiered in the ground plane  in the bottom layer?


    Is the previous inhibit area near the antenna not longer requiered?


    Do you have some reference 2 layers design to share?


    Best regards,


    1. Yes,
      it is need a “hole” of 2mm in the copper area under the module in the 4
      locations; however these “holes” are required only on top layer (layer
      where is soldered the module), in all other layers aren’t required.

      The inhibit area near the antenna is no longer required for current and future p/n

      Regarding the 2 layers design we deprecate similar solution giving below explanation in our Design Review reports:

      1. Hi,

        thanks for your answer.


        I can’t see the image you posted (it seems I don’t have the rights to access it).


        Do you have some 4 layers PCB example for GL865-QUAD?


        Thanks in advance.


        Best regards,