I have a few questions regarding the GC864 QUAD V2 hardware design:
1-Is there any App Note for the VRTC of the GC864 QUAD V2?
2-What Value should I use for the decoupling cap in the SIMVCC line? In my design
I use a dual SIM scheme with an analog multiplexer.
3-The service pin, Pin# 47 . Besides tying it to a test point how would I employ it for a FW update.
4-The Serial Port Flow Control Signals DSR,RTS,CTS, etc.. are all Active low??
5-What functionalities would I have access to with the TRACE serial port, I´m planning on using an USB to SER adapter from Future Technologies and I would like to know what debugging capabilities would be available to me by making this port available??
Service pin shall be used to upgrade the module from ASC1 (RX_TRACE, TX_TRACE). The pin shall be tied low to enable the feature only in case of a SW Update activity. It is required, for debug purpose, to be connected to a test pad on the final application.
So, tie it low before starting to update firmware on ASC1 instead of ASC0.
4. RS232 PC signal idle state is -12V and active state is +12V, on module side is vthe other way, idle is HIGH, active LOW.
5. … a lot of debugging power, but useful mostly in developing stage, if normal debugging cannot solve a situation, and only with close support with Telit team.I would say put it at least in the developing, and on field testing units.
On the "SIM Holder design guide Application Note" page 12, table 2, it states that depending on the product the value of the decoupling cap should be:
GSM/GPRS
P/N QUD7xx=100nF
GSM/GPRS
P/N QUD0xx =1000nF
UC864=10nF
I know my product is one of the first two, but which one I´m not sure, I´m using
an GC864 QUAD V2 FW Ver. 10S000530H00, Lot. No:3509
3.
Service pin shall be used to upgrade the module from ASC1 (RX_TRACE, TX_TRACE). The pin shall be tied low to enable the feature only in case of a SW Update activity. It is required, for debug purpose, to be connected to a test pad on the final application.
So, tie it low before starting to update firmware on ASC1 instead of ASC0.
4. RS232 PC signal idle state is -12V and active state is +12V, on module side is vthe other way, idle is HIGH, active LOW.
5. … a lot of debugging power, but useful mostly in developing stage, if normal debugging cannot solve a situation, and only with close support with Telit team.I would say put it at least in the developing, and on field testing units.
Ok this clears things a bit more for me, I´m planning to use a Future Tech USB to SER bridge and mux ASC0 between the USB interface and a RS-485 port. As for ASC1 I will conect it to the USB to SER bridge directly.
Finally while checking the Virtual Serial Device App Note I notesed that an RTD app is used with trace, to get this software should I request it from my distributor?
1. 2. will try to clarify with my colleagues.
5. RDT is that powerful debugging tool, you can obtain&use with a direct contact in Telit technical support, indeed obtained through your distributor. As I said, is needed only in some extreme situation, not for daily app debugging.
Got the answers: the schematic looks correct and the capacitor value should be 1000 nF.
Greetings,
I have a few questions regarding the GC864 QUAD V2 hardware design:
1-Is there any App Note for the VRTC of the GC864 QUAD V2?
2-What Value should I use for the decoupling cap in the SIMVCC line? In my design
I use a dual SIM scheme with an analog multiplexer.
3-The service pin, Pin# 47 . Besides tying it to a test point how would I employ it for a FW update.
4-The Serial Port Flow Control Signals DSR,RTS,CTS, etc.. are all Active low??
5-What functionalities would I have access to with the TRACE serial port, I´m planning on using an USB to SER adapter from Future Technologies and I would like to know what debugging capabilities would be available to me by making this port available??
1. See here.
2. Check "SIM Holder design guide Application Note" doc.
3.
So, tie it low before starting to update firmware on ASC1 instead of ASC0.
4. RS232 PC signal idle state is -12V and active state is +12V, on module side is vthe other way, idle is HIGH, active LOW.
5. … a lot of debugging power, but useful mostly in developing stage, if normal debugging cannot solve a situation, and only with close support with Telit team.I would say put it at least in the developing, and on field testing units.
1. 2. will try to clarify with my colleagues.
5. RDT is that powerful debugging tool, you can obtain&use with a direct contact in Telit technical support, indeed obtained through your distributor. As I said, is needed only in some extreme situation, not for daily app debugging.
Got the answers: the schematic looks correct and the capacitor value should be 1000 nF.