Microstrip line width doesn’t match with the 50ohm impedance

5 thoughts on “Microstrip line width doesn’t match with the 50ohm impedance

  1. Hi,
     
    I’m making a pcb project with the modem HE910. I’ve an 50ohm RF antenna connected to the PCB that has to be connected to the pad K1 of the HE910. But I’ve some doubts, let me explain before making questions.
     
    I’m using an standard PCB of 0.062" (1.5748mm) of width with 2 layers (top and bottom), the traces have a width of 0.035mm, and the relative permittivity of the dielectric is around 4.1 to 4.8 using FR4 (if I’m right). Now, with this measures, I’m suppose to make a trace of 50ohm of characteristic impedance to ensure that there won’t be mismatching losses. If my calculations are correct, the trace width has to be around 2.8mm. If you notes, that’s really wide, and even more when you realize that the space available for making an trace (from the pad K1 of the HE910) is minor than 1mm (apparently is exactly 0.7mm, the same as the pad width). So, considering that I just have 0.7mm of space for making a trace, the characteristic impedance that is obtained with this trace width is around 100ohm (that is, the double of what I’m supposed to put).
     
    So my first question is how could I fix this? 
     
    I’ve thinking in some ideas for fixing this, but I’m not sure if they would work. The first crazy idea that I think was: What if I connect the modem with the antenna via 2 traces in parallel of 100ohm of characteristic impedance? That would make that the impedance seen from the modem is the half of each, that is, 50ohm. But I’ve not seen this before, and even for me that I’m proposing this idea doesn’t sounds convincing. 
     
    Another idea (but its going to be more expensive) is making a PCB of more than 2 layers. With 3 layers and a trace width of 0.7mm, the characteristic impedance should be around 75ohm. With 4 layers and a trace width of 0.7mm, the characteristic impedance should be around 60ohm, but with 1mm of width, should be around 49ohm. So, this is a possible solution. But the Hardware user guide doesn’t specify what’s the MAX width of a trace in that particulary pad (particulary because is surrounded circularly by grounds pads, called INHIBIT WIRING), so I can’t take the chance of making a bad connection because it would make an short. If I can’t put a trace of 1mm of width, that would lead me to put another layer in the PCB. That means 5 layers, that would have 49ohm of impedance with 0.7mm of trace width. This is perfect, except by the idea that I’ve to pay for those extra layers (that I didn’t need before), and that I’ve to change my PCB layout that would take a lot of time. 
     
    I don’t have more ideas for fixing this. I calculate how much would be the losses using the line with 100ohm of impedance and, if I’m right, the losses are going to be around 9dB. These are my calculations (I’m not sure if I did it right):
     
    Supposing a load impedance of 50ohm and a transmision line of 100ohm, the reflection coefficient should be -1/3. So, the VSWR equals 2, and that leaves a loss of 9dB approx.The formulas that I used I found them here: 
     
    But what I don’t get is why the Hardware user guide says that the MAX allowable loss of a line is 0.3dB, and the same time says that the MAX allowable VSWR is 2. So, which alignment should I follow?
     
    Can you help me? 
     
    Thanks in advance. 
    1. Hi again,

       

      I’ve been thinking in another idea: What if I put a via exactly below the pad K1 of the HE910? So in this way, I could trace in the another layer a line of whatever the width I want. That could be possible? What about the characteristic impedance that has the via? It maybe could has a worse impedance that the line of 0.7mm and definitely that’s what I don’t want.

       

      What do you think about this? How do I calculate the impedance of the via?

       

      Thanks again! 

      1. Hi Andres,

         

        I usually use the follow page to calculate line inpedance:

         

        http://www1.sphere.ne.jp/i-lab/ilab/tool/cpw_g_e.htm

         

        On this page I tried to evaluate your case as per attached doc. I think you can do the job on the same layer where module is, without the use ov a via, which need a bit to calculation to be evaluated.

         

        Try to modify the values on the on line tool to see the effect, but don’t worry  a lot if the line you are designing is 0,7mm large.

         

        You have to prefer a 0,7mm track than a via.

        1. Hi Luca,

           

          Excuse me if I didn’t thank you, what you said was really useful. 

           

          But I’ve some doubts yet. Using a "Coplanar Wageguide" line could help me making the 50 ohm impedance that I need, but that would need that the width of the gap be like 0.1mm. This is extremely thin in my opinnion, what do you think about this? 

           

          I’m worried about something can go wrong. For example, what if dust drops exactly in the gap, that would make the gaps width even more thinner. Could this affect the opperation of the antenna?

           

          I was thinking in making the gap around 0.2mm, so the characteristic impedance would be around 59ohm. That would make a VSWR around 1.18. Is this a good VSWR? Could I take the chance of making my line of around 60ohm? Or is preferable to make the gap of 0.1mm width, so the impedance matches the 50ohm?

           

          Thank you a lot! 

          1. Hi Andrés,

             

            even if it’s a good practice to design a antenna line with impedance higher than 50Ohm to

            take into account impedance reduction due to process, 60 ùOhm could be a bit too high.

            But it is also a fact that 0,1 mm could be a small size, even if I think you can do it.

            The best idea should be to modify PCB style,, something likedielectric height and/or er.

             

            This is the reason why it is always suggestged a 4 layers design.